1. Field of the Invention
This invention relates to electronic circuits and, more specifically, to methods and circuitry for preventing undesirable output voltage fluctuations in integrated circuitry.
2. Brief Description of the Prior Art
Integrated circuits associated with multiple output devices often have undesirable output signal fluctuations which are caused by negative ground voltage variations, commonly termed glitches. The simultaneous switching of many multiple output devices causes excess current to be dumped into the internal ground of the circuitry. When an output of an integrated circuit is switched high to low, the charge on a capacitive load will be discharged into the chip ground according to the capacitor-current formula i=C(dv/dt). The internal ground nodes of such circuits are connected to an external ground node through a package pin which includes an inherent inductance. The external ground is fixed to zero volts. The excess current dumped into the internal ground and the external ground causes both positive and negative internal ground voltage fluctuations as described by the inductor-voltage equation V=1 di/dt. If only one output is switched, the current discharged from the load will cause only small fluctuations in chip ground. However, as the number of outputs switched increases, the chip ground movement increases significantly. This creates a problem because the input pin is tied to an external reference and does not vary with chip ground. Therefore, a large voltage as seen by the chip circuitry develops across the input circuitry as chip ground goes negative. If the input is in the low state Vi1=0.5 volts) the voltage across the input circuit (Vi1-Vgnd) may be greater than the device threshold (Vth=2 Vbe), causing the input voltage to look high momentarily and the output to glitch.
In particular, the negative ground voltage fluctuations or glitches cause transistors in the integrated circuitry to prematurely turn on when the transistor emitters are referenced to internal ground and their bases are referenced to the external voltage supply. When such transistors prematurely turn on, the output of the circuitry often begins to oscillate and creates undesirable output signal fluctuations. Such internal ground voltage fluctuations will become increasingly worse as circuit designers strive to obtain faster switching of multiple output devices.
A need has thus arisen for compensation circuitry which can prevent or eliminate undesirable output signal fluctuations caused by internal ground voltage glitches. In particular, a need has arisen for controlling the effects caused by severe negative internal ground voltage fluctuations created by rapid switching of multiple output devices. Such compensation circuitry should be useful with both transistor and diode input devices, and should be controllable as to the level of compensation control.
The prior art has attempted to remedy this problem. In one such unpublished prior art attempt, a transistor is driven by the collector of the input PNP transistor. Experimental data has shown that this type of approach causes propogation delays to increase significantly if the input has a negative undershoot just prior to switching. In a second prior art solution, as set forth in the application of Janet L. Wise, Ser. No. 881,146, filed July 2, 1986, a circuit referenced through a capacitor to Vcc is used. This circuit is very sensitive to chip Vcc and ground movement and therefore requires careful adjustment of the component values. The circuitry which limits the current through transistor 42 in said application via the collector thereof is critical because, if not controlled, it can turn on and pull base drive away from transistor 30 when the input is high and transistor 30 should be on.